1. Field of the Invention
Embodiments of the present invention generally relate to a hardware emulator, and more specifically, to a method and apparatus for designing a hardware emulation chip using a selectable fastpath topology.
2. Description of the Related Art
Hardware emulators are programmable devices used to verify hardware designs. A common method of hardware design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit(s) of the hardware. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 titled “Clustered Processors In An Emulation Engine”, which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present on an integrated circuit has increased significantly in the past several years. Hardware emulators need to improve in efficiency to keep pace with the increased complexity of integrated circuits. The speed with which a hardware emulator can emulate an integrated circuit is one of the most important benchmarks of the emulator's efficiency, and also one of the emulator's most important selling factors in the emulator market.
Hardware emulators are comprised of processors. The processors are generally arranged into groups of processors known as clusters. Each processor performs an identical set of functions, i.e., retrieving data from a memory, evaluating the data, and writing the processed result back to the memory. The processors may compute results in series, i.e., an output of one processor functions as an input to another processor. Computing results in series increases the computational efficiency of the hardware emulator by reducing the number of emulation steps required to evaluate all of the data.
Originally, hardware emulators would perform a single function within a single processor at each step of an emulation cycle. As processor speed increased, the processors were configured to operate in groups (referred to as chains) such that the output of one processor is coupled to the input of another processor and the outputs of all foregoing processors in a chain are coupled to subsequent processors in the chain. These chains of processors perform a series of functions within one step of an emulation cycle. The number of processors operating sequentially in a chain is referred to as the depth and has been known to contain as many as eight levels. These chains of processors that operate together in a single step of an emulation cycle have come to be known as a “fastpath” and the arrangement of the processors with a fastpath is known as a fastpath topology.
When emulator designer's layout an emulator that uses fastpath, they must compute a maximum clock rate that enables the fastpath depth to be completely used during each emulation step, e.g., one clock cycle. Since the time required to utilize the entire depth and produce a result varies depending upon the propagation delays of signals, the layout of the processors, the temperature of the emulator, and so on, the task of determining the number of processors to use in a fastpath is difficult. If an emulator is designed to use a fastpath having an eight level depth, but, because of the current temperature of the emulator, the propagation delays have increased and the emulator can only complete seven of the eight functions that are required before the end of the step, the emulation performed is useless and becomes unpredictable.
As such, emulator designers must predict the maximum depth that an emulator can handle. If the prediction is incorrect, as determined by chip design verification, the emulator layout must be reconfigured at great cost. For example, if it is found that certain fastpaths are too slow to utilize an eight level depth, the emulator requires the layout to be reconfigured to trim the depth to a depth that is functional, e.g., seven or six sequential processors. Such redesign is very time consuming and costly.
Therefore, there is a need in the art for a method and apparatus for reorganizing a fastpath topology without performing extensive layout redesign.